I. Overview

With the continuous increase in chip integration, the importance of packaging technology has become more prominent, and fan-out packaging has emerged as a key development path. At present, mainstream fan-out packaging processes are mainly divided into two categories: Chip-first and RDL-first, which differ in routing sequence and structural approach.

The Chip-first process can be further classified into two forms: face-down (bumps down) and face-up (bumps up). A common characteristic of both is that routing is performed only after the chip is placed. While this sequence is relatively mature, routing precision is constrained by the chip structure, making it difficult to meet the increasingly demanding requirements of high-density interconnections.

In contrast, the RDL-first process adopts a reverse approach of “routing first, chip later.” Fine redistribution layers are fabricated on the carrier in advance, and the chip is subsequently flip-chip bonded. This approach offers clear advantages: on one hand, routing without chip constraints enables finer line width and spacing, thereby improving interconnect density; on the other hand, the separation of process steps reduces overall complexity and helps improve packaging yield.

Since its initial development by NEC (now part of Renesas), the RDL-first process has evolved rapidly. Amkor has introduced solutions such as SWIFT™ and SLIM™, while TSMC and Samsung Electro-Mechanics have also actively advanced this technology. These developments are pushing RDL-first toward panel-level integration and ~2 μm line/space capabilities, laying the foundation for next-generation high-performance chip packaging.

 

II. Characteristics of the RDL-first Process

The core advantage of the RDL-first process lies in its ability to significantly improve yield. In traditional Chip-first processes, since the chip is embedded beforehand, defects occurring during subsequent routing fabrication may result in the failure of the entire package. This issue becomes particularly severe in high-density, multi-layer routing scenarios.

By contrast, RDL-first completes routing prior to chip placement. After electrical testing, only qualified regions are selected for flip-chip bonding. This effectively avoids chip waste caused by routing defects, which is especially valuable for high-cost chips.

Cost analysis indicates that when the number of chips in a package reaches three or more, the RDL-first process becomes more cost-effective. Therefore, it is currently widely applied in complex multi-chip system integration. As chip costs continue to rise and the process becomes further optimized, its application scope is expected to expand.

However, it should be noted that for packages with fewer chips, the required temporary bonding and debonding steps introduce additional costs. In addition, this process typically requires chips to be pre-bumped; otherwise, flip-chip alignment becomes significantly more challenging.

 

III. RDL-first Process Technologies

A key challenge in the RDL-first process is how to complete routing on a temporary carrier and then successfully release the final package. To address this, the industry has developed three mainstream technical approaches. Their primary differences lie in how the dielectric (insulating) layers are formed and how the carrier is removed.

 

1. Deposition–Grinding Method

This is the most direct and fundamental approach. First, dielectric layers and copper routing layers are sequentially fabricated on a smooth temporary carrier (such as glass or silicon) using Physical Vapor Deposition (PVD)—a process that deposits thin atomic films in a vacuum environment.

After completing all routing structures and attaching the chips, the entire carrier is gradually removed through mechanical grinding (similar to precision polishing). Eventually, a standalone packaged structure is obtained.

 

The process of performing RDL-first fan-out using PVD

 

2. Electroplating–Laser Method (Mainstream / Widely Used Route)

This is currently the most mainstream and advanced approach in the industry. It typically uses glass as the temporary carrier, due to its transparency to specific laser wavelengths.

First, a temporary bonding adhesive is spin-coated onto the glass carrier, followed by the fabrication of routing layers on top of the adhesive. Copper routing is usually formed using a “electroplating + etching” process: copper is first plated, then patterned using photolithography and etching, achieving higher precision.

After completing all processes, a laser is applied from the backside of the glass carrier. The laser, with a specific wavelength, selectively decomposes the bonding adhesive, enabling clean, non-contact laser debonding. This allows the finished package to be removed intact, while the glass carrier can be reused.

 

Key steps in completing the RDL-first process on a glass substrate

 

3. Hybrid Integration Method

As the name suggests, this approach is a flexible combination of the previous two methods. For example, different materials and processes may be used for bottom and top routing layers to balance performance and cost.

Alternatively, for certain complex structures, high-precision regions may adopt the electroplating–laser method, while less critical areas use the deposition–grinding method. This approach offers the highest level of customization and is well-suited for advanced packaging with complex structures, multifunctionality, and heterogeneous integration.

However, it also involves the greatest challenges in process development and management complexity.

 

Hybrid RDL FOWLP Process Flow

 

IV. Summary

The future development of the RDL-first process is evolving toward greater precision, higher complexity, and improved cost efficiency, with the core goal of supporting next-generation high-density, high-performance chips.

Future technological breakthroughs will primarily focus on three dimensions: 3D integration, miniaturization, and scalability. Technologically, the industry is shifting from planar routing to three-dimensional routing, enabling multi-layer metal interconnect stacking for high-density 3D integration of complex chips such as chiplet-based architectures—similar to constructing a miniature multi-level interchange system within the package.

At the same time, line width and spacing will continue to shrink, advancing toward 2 μm and beyond, achieving chip-level precision to support higher bandwidth and smaller form factors.

From an industrial perspective, the primary driving force is cost reduction. A key pathway is the transition from wafer-level manufacturing to panel-level manufacturing, where large rectangular substrates—similar to printed circuit boards—are used to produce many packaging units simultaneously. This scale effect significantly reduces the packaging cost per chip.

In addition, advancements in materials and carrier technologies, such as reusable carriers, play a crucial role in improving efficiency and reducing costs.

Overall, the RDL-first process is becoming deeply integrated with the trend of heterogeneous integration, and its evolution will directly determine the integration level, performance, and final cost of future high-performance chips.

 

V. FAQs

1. What is the main difference between RDL-first and Chip-first packaging?

The primary difference lies in the process sequence. In RDL-first, redistribution layers (RDL) are fabricated before chip placement, enabling higher routing precision and better yield. In contrast, Chip-first embeds the chip first and performs routing afterward, which may limit routing density due to chip structure constraints.

 

2. Why does the RDL-first process achieve higher yield?

RDL-first improves yield because routing is completed and electrically tested before chip bonding. Only known-good areas are selected for chip placement, reducing the risk of wasting expensive chips due to routing defects.

 

3. What are the typical applications of RDL-first packaging?

RDL-first is mainly used in multi-chip integration, high-performance computing (HPC), AI processors, and advanced heterogeneous integration systems, where high interconnect density and reliability are critical.

 

4. What are the limitations of the RDL-first process?

Despite its advantages, RDL-first has some limitations:

        Additional temporary bonding and debonding steps increase process complexity

        Higher cost for low chip-count packages

        Requires pre-bumped wafers, adding preparation steps

 

5. What materials are commonly used in RDL-first processes?

Typical materials include:

        Glass or silicon carriers for temporary substrates

        Polymer dielectric layers for insulation

        Copper (Cu) for redistribution wiring

        Temporary bonding adhesives for carrier attachment and release

 

6. What is the future trend of RDL-first technology?

RDL-first is evolving toward:

      Ultra−fineline/space(<2μm) for higher density

        3D interconnect architectures for chiplet integration

        Panel-level packaging (PLP) for cost reduction

        Reusable carrier technologies for improved sustainability and efficiency

 

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