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74LVC16373ADGV-Q1J
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74LVC16373ADGV-Q1J Overview
The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Bus hold on the data inputs eliminates the need for external pull - up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Overvoltage tolerant inputs to 5.5 V
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power dissipation
- MULTIBYTE flow-through standard pinout architecture
- Multiple low inductance supply pins for minimum noise and ground bounce
- Direct interface with TTL levels
- All data inputs have bus hold (74LVCH16373A-Q100 only)
- I
- OFF
- Complies with JEDEC standards:
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- JESD8-7A (1.65 V to 1.95 V)
- JESD8-5A (2.3 V to 2.7 V)
- JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection:
- MIL-STD-883, method 3015 exceeds 2000 V
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
- CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
- MIL-STD-883, method 3015 exceeds 2000 V
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
- CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Product Parameters
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id
http://www.data.nexperia.com/id/plm/salesItem/935690793118
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name
74LVC16373ADGV-Q1J
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packingQuantity
2,500
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nc12
935690793118
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packingDescription
Reel 13" Q1/T1
Technical Documents
Other distributor's price
Distributor | Part # | Mfg. | Description | Price |
---|---|---|---|---|
74LVC16373ADGV-Q1J | Nexperia | 74LVC16373ADGV-Q100/SOT480/TSS |
2500---$0.6141 |
|
74LVC16373ADGV-Q1J | Nexperia | Latches 74LVC16373ADGV-Q100/SOT480/TSS |
1---$1.4200 10---$1.2800 25---$1.2100 100---$0.9990 250---$0.9330 500---$0.8250 1000---$0.6510 2500---$0.5930 5000---$0.5730 |
|
74LVC16373ADGV-Q1J | Nexperia |
2500---$0.4550 |
||
74LVC16373ADGV-Q1J | Nexperia | Latch, D Type, -40 To 125Deg C, Logic Family/Base Number:74Lvc16373A, Latch Type:D Type, Ic Output Type:Tri State Non Inverted, Propagation Delay:5.5Ns, Output Current:-, Logic Case Style:Tssop, No. Of Pins:48Pins, Supply Voltage Rohs Compliant: Yes |Nexperia 74LVC16373ADGV-Q1J |
1---$1.1600 10---$1.0400 25---$0.9860 50---$0.8980 100---$0.8100 250---$0.7570 500---$0.6690 1000---$0.5480 |
|
74LVC16373ADGV-Q1J | Nexperia | D-Type Transparent Latch 16-Channel 5V Tolerant Input/Output 3-State 48-Pin TSSOP T/R - Tape and Reel (Alt: 74LVC16373ADGV-Q1J) |
2500---$0.7040 5000---$0.6850 10000---$0.6660 15000---$0.6470 20000---$0.6279 25000---$0.6089 250000---$0.5899 |
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