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74LVC1G175GW-Q100H
  • 74LVC1G175GW-Q100H

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74LVC1G175GW-Q100H Overview

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74LVC1G175GW-Q100H

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Overvoltage tolerant inputs to 5.5 V
  • CC
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • I
  • OFF
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
  • JESD8-7 (1.65 V to 1.95 V)
  • JESD8-5 (2.3 V to 2.7 V)
  • JESD8C (2.7 V to 3.6 V)
  • JESD36 (4.5 V to 5.5 V)
  • JESD8-7 (1.65 V to 1.95 V)
  • JESD8-5 (2.3 V to 2.7 V)
  • JESD8C (2.7 V to 3.6 V)
  • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
  • MIL-STD-883, method 3015 exceeds 2000 V
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
  • MIL-STD-883, method 3015 exceeds 2000 V
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

Product Parameters

  • id

    http://www.data.nexperia.com/id/plm/salesItem/935301507125

  • name

    74LVC1G175GW-Q100H

  • packingQuantity

    3,000

  • nc12

    935301507125

  • packingDescription

    Reel Pack, 7" Q3/T4

Technical Documents

Other distributor's price

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arrow 74LVC1G175GW-Q100H Nexperia Flip Flop D-Type Pos-Edge 1-Element Automotive 6-Pin TSSOP T/R

1---$0.3901

10---$0.3000

25---$0.2700

100---$0.1884

250---$0.1579

500---$0.1280

1000---$0.0978

3000---$0.0947

6000---$0.0938

digikey 74LVC1G175GW-Q100H Rochester Electronics LLC IC FF D-TYPE SNGL 1BIT 6TSSOP

3000---$0.0943

6000---$0.0890

15000---$0.0812

30000---$0.0759

75000---$0.0741

verical 74LVC1G175GW-Q100H Nexperia Flip Flop D-Type Pos-Edge 1-Element Automotive 6-Pin TSSOP T/R

117---$0.1884

250---$0.1579

500---$0.1280

1000---$0.0978

3000---$0.0969

avnet 74LVC1G175GW-Q100H Nexperia Flip Flop D-Type Pos-Edge 1-Element 6-Pin TSSOP T/R - Tape and Reel (Alt: 74LVC1G175GW-Q100H)

15000---$0.0823

21000---$0.0801

36000---$0.0778

75000---$0.0756

150000---$0.0734

750000---$0.0712

1500000---$0.0689

mouser 74LVC1G175GW-Q100H Nexperia Flip Flops 74LVC1G175GW-Q100/SOT363/SC-88

1---$0.5600

10---$0.4180

100---$0.2380

500---$0.1580

1000---$0.1210

3000---$0.1040

9000---$0.0830

24000---$0.0780

45000---$0.0740

future 74LVC1G175GW-Q100H Nexperia 74LVC Series 5.5 V Surface Mount Single D-Type Flip-Flop with Reset - SOT-363

3000---$0.0828

6000---$0.0807

12000---$0.0787

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45000---$0.0742

newark 74LVC1G175GW-Q100H Nexperia Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant: Yes |Nexperia 74LVC1G175GW-Q100H

1---$0.4200

10---$0.3190

25---$0.2880

50---$0.2440

100---$0.1990

250---$0.1670

500---$0.1360

1000---$0.1040