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CDCVF857DGGR

  • CDCVF857DGGR

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CDCVF857DGGR Overview

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

Features

  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
  • Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
  • AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
  • Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
  • ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
  • Spectrum Input; Data Randomization and
  • Shuffling on Serial Link; Deserializer Provides
  • Adjustable PTO (Progressive Turnon) LVCMOS
  • Outputs
  • LVDS Transmission Path
  • Individual Power-Down Controls for Both
  • Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
  • TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
  • DS90C241/DS90C124
CDCVF857DGGR
CDCVF857DGGR

Product Parameters

  • genericPartNumber

    CDCVF857

  • partDescription

    2.5-V phase lock loop DDR clock driver

  • statusDescription

    This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.

  • packageQtyCarrier

    2000|LARGE T&R

  • orderablePartNumber

    CDCVF857DGGR

  • statusDisplay

    ACTIVE

  • packageQuantity

    2000

  • packagePins

    TSSOP (DGG)|48

Technical Documents

  • AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B)Details>>

  • LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)Details>>

  • DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)Details>>

  • AN-1807 FPD-Link II Display SerDes Overview (Rev. B)Details>>

  • Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)Details>>

Related Products

Other distributor's price

Distributor Part # Mfg. Description Price
arrow CDCVF857DGGR Texas Instruments Zero Delay Buffer 10-Out Differential 48-Pin TSSOP T/R

2000---$4.7820
digikey CDCVF857DGGR Rochester Electronics LLC IC 2.5V PHASE LOCK LOOP 48-TSSOP

2000---$4.7658
verical CDCVF857DGGR Texas Instruments Zero Delay Buffer 10-Out Differential 48-Pin TSSOP T/R

2---$6.4120

10---$6.0690

25---$5.8910
mouser CDCVF857DGGR Texas Instruments Clock Drivers & Distribution 2.5V Ph Lock Loop DDR Clock Driver

2000---$5.6400

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