Features

• S08 CPU
• 40 MHz core speed, 20 MHz bus speed on S08 CPU
• HC08 instruction set with added BGND instruction
• On-Chip Memory
• Up to 128 KB flash read/program/erase over full operating voltage and temperature
• Up to 2 KB EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dualpage erase sector; program and erase while executing flash; erase abort
• Up to 8 KB RAM (16:1 flash/RAM, ratio better than competition)
• Power Saving Modes
• Two very low-power stop modes
• Very low-power, real-time interrupt for use in run, wait and stop modes
• Clock Source Options
• Oscillator (XOSC)—Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz–38.4 kHz or 1 MHz–16 MHz
• Multi-purpose clock generator (MCG)–PLL and FLL modes; internal reference clock with trim adjustment; external reference with oscillator/resonator options
• System Protection
• Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock
• Low-voltage detection with reset or interrupt; selectable trip points
• Illegal opcode detection with reset
• Illegal address detection with reset
• Flash block protect
• EEPROM block protect
• Peripherals
• ACMPx—Analog comparators with selectable interrupt on rising, falling or either edge of comparator output; compare option to fixed internal bandgap reference voltage
• MSCAN—CAN protocol—Version 2.0 A, B; standard and extended data frames; support for remote frames; five receive buffers with FIFO storage scheme; flexible identifier acceptance filters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit
• SCIx—SCI(s) with LIN 2.0 Protocol and SAE J2602 compliance;
• leader
• SPI—Full-duplex or single-wire bi-directional; double-buffered transmit and receive; leader or follower mode; MSB-first or LSB-first shifting
• I
• 2
• C—Up to 100 kbps with maximum bus loading; multi-controller operation; programmable target address; interrupt-driven, byte-by-byte data transfer; broadcast mode enabled
• TPMx—One 6-channel (TMP1) and one 2-channel (TPM2); selectable input capture, output compare or buffered edge-aligned PWM on each channel
• RTC (Real-time counter)—8-bit modulus counter with binary or decimal-based prescaler; external clock source for precise time base, time-of-day calendar or task scheduling functions; free running, on-chip, low-power oscilator (1 kHz) for cyclic wake-up without external components
• Development Support
• Single-wire background debug (BDM) interface
• On-chip, in-circuit emulation (ICE) with real-time bus capture
• Input/Output
• 87 general-purpose I/O pins and one input-only pin
• 32 interrupt pins with selectable polarity on each pin
• Hysteresis and configurable pull-up device on all input pins
• Configurable slew rate and device strength on all output pins
• Package Options
• 100 LQFP 14 x 14 mm
• 64-pin low-profile quad flat pack (LQFP)—10 x 10 mm
• 48-pin LQFP—7 x 7 mm
• 32-pin LQFP—7 x 7 mm
• Miscellaneous
• EMC performance
• Wide operating voltage range: 2.7V–5.5V
• Background Debugging System
• On-chip BDM
• Package
• Pin-compatible with SH, QG family
• Product Longevity Program
• This product is included in our product longevity program, with assured supply for a minimum of 15 years after launch