Features

• High-performance e200z4d dual core
• 32-bit Power Architecture technology CPU
• Core frequency as high as 120 MHz
• Dual issue five-stage pipeline core
• Variable Length Encoding (VLE)
• Memory Management Unit (MMU)
• 4 KB instruction cache with error detection code
• Signal Processing Engine (SPE)
• 32-bit Power Architecture technology CPU
• Core frequency as high as 120 MHz
• Dual issue five-stage pipeline core
• Variable Length Encoding (VLE)
• Memory Management Unit (MMU)
• 4 KB instruction cache with error detection code
• Signal Processing Engine (SPE)
• Memory available
• 2 MB flash memory with ECC
• 192 KB on-chip SRAM with ECC
• Built-in RWW capabilities for EEPROM emulation
• 2 MB flash memory with ECC
• 192 KB on-chip SRAM with ECC
• Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: Lock step mode and Fail-safe protection
• Sphere of Replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
• Fault Collection and Control Unit (FCCU)
• Redundancy Control and Checker Unit (RCCU) on outputs of the SoR connected to FCCU
• Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
• Boot-time Built-In Self-Test for ADC and flash memory triggered by software
• Replicated safety enhanced watchdog
• Replicated junction temperature sensor
• Non Maskable Interrupt (NMI)
• 16-region Memory Protection Unit (MPU)
• Clock Monitoring Units (CMU)
• Power Management Unit (PMU)
• Cyclic Redundancy Check (CRC) unit
• Sphere of Replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
• Fault Collection and Control Unit (FCCU)
• Redundancy Control and Checker Unit (RCCU) on outputs of the SoR connected to FCCU
• Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
• Boot-time Built-In Self-Test for ADC and flash memory triggered by software
• Replicated safety enhanced watchdog
• Replicated junction temperature sensor
• Non Maskable Interrupt (NMI)
• 16-region Memory Protection Unit (MPU)
• Clock Monitoring Units (CMU)
• Power Management Unit (PMU)
• Cyclic Redundancy Check (CRC) unit
• Decoupled Parallel mode for high performance use of replicated cores
• Nexus Class 3+ interface
• Interrupts
• Replicated 16-priority controller
• Replicated 16-channel eDMA controller
• Replicated 16-priority controller
• Replicated 16-channel eDMA controller
• GPIOs individually programmable as input, output or special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units: Four 16-bit channels per module
• Communications interfaces
• 2 LINFlexD channels
• 3 DSPI channels with automatic chip select generation
• 3 FlexCAN interfaces (2.0B Active) with 32 message objects
• FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
• 2 LINFlexD channels
• 3 DSPI channels with automatic chip select generation
• 3 FlexCAN interfaces (2.0B Active) with 32 message objects
• FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
• Two 12-bit Analog-to-digital Converters (ADC)
• 16 input channels
• Programmable Cross Triggering Unit (CTU) to synchronize ADCs conversion with timer and PWM
• 16 input channels
• Programmable Cross Triggering Unit (CTU) to synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART/FlexRay Bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C