Features

• Performance
• Up to 2 x Power Architecture e200z4 dual issue 32-bit cores
• Up to 160 MHz operation
• Single precision floating point operation
• 8 KB instruction cache and 4 KB data cache
• Variable length encoding (VLE) for significant code density improvement
• Up to 1 x Power Architecture e200z2 single issue 32-bit core
• Up to 80 MHz operation
• Variable length encoding
• Flash and SRAM
• Up to 6 MB Flash memory with error correction coding (ECC)
• Three port Flash controller
• Up to 768 KB of SRAM with ECC
• Three RAM ports
• Connectivity and Communications
• 10/100 Ethernet that supports 1588 and MII/RMII
• Multiple queue AVB support
• Optional 2
• nd
• MediaLB (MLB150) supporting 3-pin and 6-pin interface and speed grades up to 2048 fs
• One USB 2.0 Host (USBSPH) and one USB 2.0 Device (USBOTG) with ULPI support
• One dual-channel FlexRay Controller with 128 message buffer
• 18 LINFlex (1 xPrimary/Secondary, 17xPrimaries)
• Eight enhanced FlexCAN modules with CAN FD support and configurable buffers
• Each instance supports DMA on RxFIFO
• Low-power mode with Pretended Networking support on a single FlexCAN module
• One Secure Digital Hardware Controller (μSDHC) supporting Secure Digital Input Output (SDIO) and MMC
• Four inter-IC communication interface (I2C) modules
• Three Synchronous Audio Interface (SAI) capable of supporting six stereo audio channels
• Four Deserial Peripheral Interface (DSPI) modules with supporting external SPI controlled lamp/LED drives
• Six Serial Peripheral Interface (SPI) modules
• Low Power
• Low-Power Unit (LPU) mode that allows e200z2 core to bypass the crossbar when in low power modes
• Only a subset of the device is powered in LPU mode
• Three analog comparators providing up to 24 compare inputs
• Periodic monitoring routines can be fully handled in STANDBY mode
• Pretended Networking support through advanced CAN filtering, wakeup capabilities and availability in LPU mode
• Safety and Security
• Hardware Security Module (HSM) enabling advanced security management
• Designed to ISO 26262 process, targeting higher level ASIL systems
• End-to-end Error Correction Coding (ECC)
• User selectable Memory Built-In Self Test (MBIST) and Logic BIST (LBIST)
• Can be enabled to run out of reset conditions, runtime and can be disabled
• Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts and reset depending on criticality
• Voltage and clock monitors