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KSZ9031RNXIA

  • KSZ9031RNXIA

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KSZ9031RNXIA Overview

The KSZ9031 is a completely integrated triple-speed (10Base-T/100Base-TX/1000Base-T) Ethernet physical-layer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.The KSZ9031MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000Mbps or 10/100Mbps. The KSZ9031RNX provides the reduced gigabit media independent interface (RGMII).The KSZ9031 reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.The KSZ9031 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and the board. The LinkMD TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths.The standard KSZ9031RNX is available in the 48-pin, lead-free QFN package, and the AEC-Q100 automotive qualified parts, KSZ9031RNXUB-VAO and KSZ9031RNXVB-VAO, are available in the 48-pin lead-free WQFN package. The KSZ9031MNX is available in a 64-pin, lead-free QFN package.Microchip's complimentary and confidential LANCheck online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

ksz9031rnxia-1

Features

  • Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver
  • KSZ9031Mxx feature GMII/MII standard interface with 3.3V/2.5V/1.8V tolerant I/Os
  • KSZ9031Rxx feature RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths
  • GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os
  • Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
  • On-chip termination resistors for the differential pairs
  • On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
  • Jumbo frame support up to 16KB
  • 125MHz Reference Clock Output
  • Energy-detect power-down mode for reduced power consumption when the cable is not attached
  • Wake-on-LAN (WOL) support with robust custom-packet detection
  • AEC-Q100 qualified for automotive applications (KSZ9031RNXUB-VAO, KSZ9031RNXVB-VAO)
  • Programmable LED outputs for link, activity, and speed
  • Baseline wander correction
  • LinkMD  TDR-based cable diagnostic to identify faulty copper cabling
  • Parametric NAND tree support to detect faults between chip I/Os and board
  • Loopback modes for diagnostics
  • Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation
  • Automatic detection and correction of pair swaps, pair skew, and pair polarity
  • MDC/MDIO management interface for PHY register configuration
  • Interrupt pin option
  • Power-down and power-saving modes
  • Operating voltages:
  • Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator)
  • VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
  • Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
  • Available in 48-pin QFN (7mm x 7mm) and 64-pin QFN (8mm x 8mm) packages
KSZ9031RNXIA
KSZ9031RNXIA

Product Parameters

  • Device Weight (g)

    0.129500

  • Package Width

    7x7x0.9mm

  • JEDEC Indicator

    e3

  • Shipping Weight (grams)

    0.961539

  • Solder Composition

    Matte Tin

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